1. Field of the Invention
The present invention relates to stacked transistor structures, such as can be used in high density three-dimensional (3D) memory devices, and memory devices utilizing such structures.
2. Description of Related Art
High density three-dimensional (3D) memory devices include stacked multiple planes of memory cells, and peripheral circuits. The peripheral circuits can include circuitry for example that controls the memory cells for program, erase and read operations. Metal layers or other conductive or semiconductive layers can electrically connect the peripheral circuits to the memory cells. Typically, the peripheral circuits are manufactured in CMOS (complementary metal-oxide-semiconductor) technology, while the stacked multiple planes of memory cells are manufactured in different technologies such as charge trapping memory technologies that requires process steps that are different from those used to form the peripheral circuits.
It is desirable to provide a technology for a three-dimensional (3D) memory device to facilitate integration of stacked multiple planes of memory cells with peripheral circuits of the three-dimensional (3D) memory device.